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MarkI Synthesizer Module
Software
Hardware Platform
Python Oscilloscope
from SoftOscilloscope import SerialPlot
plot = SerialPlot('/dev/ttyUSB0',921600)
plot.start()
Direct Serial Console
- Putty, /dev/ttyUSB0, 921600 baud
- Cygwin commands:
cat < /dev/ttyS2
cat < /dev/ttyS2 > trap_log.csv
stty -F /dev/ttyS2 -a
screen /dev/ttyS1 1000000
tee </dev/ttyS3 serial-log.txt
- Minicom, Serial Terminal for Ubuntu
- Teraterm Home, Download
- gtkterm for Ubuntu
- Default pins on Nucleo STM327476RG for serial console:
- This actually works
- STLink board, RX, green, FTDI-232R, yellow, pin 5
- STLink board, RX, blue, FTDI-232R, yellow, pin 4
- Should be these, but had problems!
- PA_2, D1, Serial2_TX = UART_TX, CN10 "TX", green, 232R pin 5, Yellow, RXD
- PA_3 = UART_RX, CN10 "RX", blue, 232R pin 4, Orange, TXD
- GND = GND, ?, ?, 232R pin 1, GND
GPIO-controlled Amplifier Current Sensors Voltage Sensors Keyboard
GPIO-controlled Amplifier/Speaker, AMP-HB-01
Instance Name
|
Chip Pin
|
Board Label
|
Data Type
|
Purpose
|
AMP1_A
|
PA_10
|
D2
|
DigitalOut
|
direction 1
|
AMP1_B
|
PB_3
|
D3
|
DigitalOut
|
direction 2
|
PWM_OUT
|
PD_7
|
D7
|
PwmOut
|
PWM out
|
Current sensors
Instance Name
|
Chip Pin
|
Board Label
|
Color
|
Purpose
|
meas_curr[ 0 ]
|
PA_0
|
A0
|
Black
|
Current Sense 1
|
meas_curr[ 1 ]
|
PA_1
|
A1
|
White
|
Current Sense 2
|
meas_curr[ 2 ] |
PA_4
|
A2
|
Blue
|
Current Sense 3
|
|
|
|
|
Current Sense 4
|
Voltage sensors
Instance Name
|
Chip Pin
|
Board Label
|
Data Type
|
Purpose
|
|
PB_0
|
A3
|
Voltage Sense 1
|
Voltage across capacitor storage
|
Keyboard, KEY-CHROM-01
Instance Name
|
Chip Pin
|
Board Label
|
Data Type
|
Purpose
|
|
|
|
|
D8
|
|
|
|
|
|
|
D9
|
|
|
|
|
|
|
D10
|
|
|
|
|
|
|
D11
|
|
|
|
|
Onboard voltage regulator, LD1117
Voltage Sense 2
Voltage Sense 3
Voltage Sense 4
Inputs, Control Voltages
Control Voltage 1
Control Voltage 2
Control Voltage 3
Control Voltage 4
Notes on PWM:
- For PWM-controlled speaker:
26.3.13 Combined PWM mode
Combined PWM mode allows two edge or cent
er-aligned PWM signals to be generated with
programmable delay and phase shift between re
spective pulses. While the frequency is
determined by the value of the TIMx_ARR regi
ster, the duty cycle and delay are determined
by the two TIMx_CCRx registers. The resulti
ng signals, OCxREFC, are made of an OR or
AND logical combination of two reference PWMs:
Manual section 26.3.15
Complementary outputs and dead-time insertion
The advanced-control timers (TIM1/TIM8)
can output two complementary signals and
manage the switching-off and the switching-on instants of the outputs.
26.3.12 Asymmetric PWM mode
Asymmetric mode allows two center-aligned PWM signals to be generated with a
programmable phase shift. While the frequency is determined by the value of the
TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of
TIMx_CCRx register. One register controls the PWM during up-counting, the
second during down counting, so that PWM is adjusted every half PWM cycle:
–
OC1REFC (or OC2REFC) is contro
lled by TIMx_CCR1 and TIMx_CCR2
–
OC3REFC (or OC4REFC) is contro
lled by TIMx_CCR3 and TIMx_CCR4
Control Voltage 1
mbed boot faster
(Current uses clock "MCO" (external, from debugger board?!).
XTAL1 is not populated.
Must add XTAL.
Must change clock code to boot from external xtal.
https://duckduckgo.com/?q=mbed+faster+boot+time
https://developer.mbed.org/forum/helloworld/topic/1222/
mbed
https://developer.mbed.org/handbook/How-mbed-works
https://developer.mbed.org/handbook/mbed-interface
https://developer.mbed.org/handbook/mbed-Compiler
https://developer.mbed.org/questions/
Make mbed boot faster
https://developer.mbed.org/users/kenjiArai/notebook/nucleo-series-clock-structure-and-xtal-oscillation/
https://developer.mbed.org/questions/70461/Why-does-this-nucleo-board-lack-a-crysta/
http://stm32f4-discovery.net/2015/01/properly-set-clock-speed-stm32f4xx-devices/
https://developer.mbed.org/search/?q=stm32l476+startup
https://developer.mbed.org/questions/67987/STM32L476-LSE-startup-issues/
https://developer.mbed.org/users/Sissors/code/WakeUp/
http://www.st.com/content/ccc/resource/technical/document/application_note/group0/93/81/9b/8d/2f/09/4a/e8/DM00125306/files/DM00125306.pdf/jcr:content/translations/en.DM00125306.pdf
http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32l4-series/stm32l4x6/stm32l476rg.html?icmp=pf260095_pron_pr_feb2015&sc=stm32l476-pr
mbed CAN bus issue with exporting makefiles
(needed to change clock possibly?)
https://developer.mbed.org/questions/70481/Nucleo-F303K8-ANY-project-fails-to-compi/
https://developer.mbed.org/questions/70477/Latest-mbed-lib-causing-issues-with-Nucl/
https://groups.google.com/forum/#!topic/mbed-devel/3OG2D7iiik0
https://developer.mbed.org/handbook/Getting-Started-mbed-Exporters
https://developer.mbed.org/handbook/Exporting-to-offline-toolchains
https://developer.mbed.org/handbook/Exporting-to-Make
STM32L476 and dev boards
https://www.tindie.com/products/onehorse/dragonfly-stm32l4-development-board/
http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32l4-series/stm32l4x6/stm32l476rg.html
http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-l476rg.html
http://www.emcu.it/STM32L4xx/STM32L4xx.html
http://www.emcu.it/STM32L4xx/STM32L4xx.html#NUCLEO-L476RG
http://www.mouser.com/new/stmicroelectronics/stm-stm32l4-mcu-fpu/
Cortex M4 General
https://github.com/matianfu/arabesque/wiki/STM32F4-Development-Environment-Setup-on-Ubuntu
http://askubuntu.com/questions/399133/how-to-install-arm-none-eabi-gdb-gdb-openocd-gcc-for-stm32-toolchain
EEL_CPU_A32_01 on gdrive
Original Synthesizer Module .... ( alternate link? )
Main additions to MarkII of this board are:
1. Circuit board layout overhaul
2. Components overhaul
Components Overhaul
40-pin sockets:
http://www.digikey.com/product-detail/en/ED40DT/ED3048-5-ND/4147604
http://www.digikey.com/product-detail/en/A40-LC-TT/AE10008-ND/821762
http://www.digikey.com/product-detail/en/243-40-1-06/1175-1481-ND/3441577
For terminal selection, see: Terminal Block Research
Done
Big changes
Physical
- Mode potentiometer removed
- Regulator moved off-board
- Added test points
- Terminal headers shrunk
- Added Mounting Holes
Electronic
- Added DIP switches for log mode / patch select
- Added dual digital audio out headers
- Changed 4.7uF bypass cap to 0.1uF
- Added 6-pin keyboard header
- Added ground plane
- Correct error in VCC/VDD
- Added 6-pin AVRISP header. References
Details
- More space around connectors
- Correct labels on parts
- All pins broken out to headers
- Reduced resistor size
- Added power terminals to keyboard
Todo
update chalkswitch drawing that Ayah made in 2006 :)
Notes:
Using AVR ISP MkII programmer on PC:
http://www.visualmicro.com/post/2014/01/17/AvrIsp-MkII-Usb-Driver-for-Arduino.aspx
avrdude -p m32 -c stk500 -P usb:02:98 -v -v -U lfuse:r:lfusefile.hex:i
STLink board, RX, green, FTDI-232R, yellow, pin 5
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